Logic circuitry has been developed to implement a floating point multiply-accumulate operation (FMAC). This operation performs on three operands (A, B, C) the operation A*B+C. The FMAC operation is useful in that it can be used to implement both addition and multiplication in logic circuitry. In particular, for an add operation, the operand A is set to a value one. For a multiply operation, the operand C is set to a value zero.
For example, FIG. 1 is a diagram of a prior art circuit 10 for use in implementing an FMAC operation. In circuit 10, three latches 12, 14, and 16 contain three 17-bit operands A, B, and C. The values of those operands are input to a first carry-save adder (CSA) 18. The result of the first CSA 18 is input to a second CSA 20 along with the value of a constant received on line 22. Finally, the output of the second CSA adder 20 is input to a carry-lookahead adder (CLA) 24, which performs an add operation and outputs a resulting shift value on line 26 for use in an FMAC operation.
The shift value is used to line up the mantissas for the add portion of the FMAC operation. The floating point numbers used by the FMAC operation are each expressed as a mantissa and an exponent. The result of the multiply operation (A*B) produces a product that typically has a different exponent than the exponent of operand C. The FMAC operation uses the shift value to shift, and hence “line up,” the mantissa of operand C for adding it with the mantissa of the A*B product. Although the mantissa of operand C is shifted, the mantissa of the A*B product could alternatively be shifted to perform the add operation. Calculating the shift value and performing the shifting of the mantissa of operand C occur during the multiply operation. The format of floating point numbers, the addition of floating point numbers and the multiplication of floating point numbers are known in the art.
Using these multiple stages within circuit 10 to produce the shift value can introduce a significant amount of delay in performing the FMAC operation. Accordingly, a need exists for a faster method of implementing an FMAC operation.